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TDA8204B
NICAM DECODER
. . . . . . .
HIGHLY INTEGRATED TWO-CHIP SOLUTION FOR NICAM DEMODULATION (using TDA8205 QSPK) DATA AND SOUND RECOVERY ACCORDING TO EBU SPB 424 SPECIFICATIONS I2S INTERFACE FOR DIGITAL AUDIO PURPOSES (14-bit samples, 32kHz word select clock, 896kHz serial clock) 4 TIMES UP SAMPLING DIGITAL FILTER AND NOISE SHAPER I2C INTERFACE FOR MICROCONTROLLER SOFTWARE DRIVE PAY TV APPLICATION CAPABILITIES AUTOMATIC ERROR MONITORING (programmable error rate limit)
SHRINK 42 (Plastic Package) ORDER CODE : TDA8204B
PIN CONNECTIONS
GND DACDR DACDL SERI
1 2 3 4 5 6 7 8 9 10 11 12 13
42 41
CK11648 TEST2 CK728 NDI GND TEST TEST1 SEL0 SEL1 DV
40
39 38 37 36
VDD
RSW HA0 TEST0 US2 US1 US0 SCL SDA SD
35
34 33 32 31 30
VDD
ADV PDV FID DDO DDI GND
14
15 16 17 18
29
28 27 26 25
DESCRIPTION The TDA8204B performs two main functions, first one is NICAM decoding, second one is audio signal recovery (DAC) combined with audio signal switching (Matrix). An I2S output is provided for digital audio when required and all functions of both the TDA8204B and the TDA8205 are accessed via an on-chip I2C bus interface. The I2S interface can be used as an input for converting to analog some I2S digital sound.
November 1994
SCK WS
VDD
C4 C3 C2 C1
MUTE
RESET
8204B-01.EPS
19
20 21
24
23 22
ER GND
1/12
TDA8204B
PIN ASSIGMENT
Pin No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 PIn Name GND DACDR DACDL SERI VDD RSW HA0 TEST0 US2 US1 US0 SCL SDA SD SCK WS VDD C4 C3 C2 C1 Function Ground PWM Data Output Right PWM Data Output Left Inter Chip Serial Bus Output +5V Supply Reserve Sound Switch Status/Control Hardware Address Selection To be connected to VDD or GND User bit 2 (input) User bit 1 (output) User bit 0 (output) I2C Bus Clock 2 I C Bus Data I2S Bus Data 2 I S Bus Clock I2S Bus Word Select +5V Supply Application Control Bit 4 Flag Application Control Bit 3 Flag Application Control Bit 2 Flag Application Control Bit 1 Flag Pin No 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Pin Name GND ER RESET MUTE GND DDI DDO FID PDV ADV VDD DV SEL1 SEL0 TEST1 TEST GND NDI CK728 TEST2 CK11648 Function Ground Error Monitor Flag Output Reset NICAM Mute Ground Descrambled Data Input Descrambled Data Output Frame Identification Flag Output Parity Data Valid Flag Output Additional Data Valid Flag Output +5V Supply Data Valid Flag Output Language Selection 1 Input Language Selection 0 Input Not to be connected To be connected to GND Ground NICAM Data Input 728kHz bit Clock Output Not to be connected 11.648MHz bit Clock Input
BLOCK DIAGRAM
SEL0 RSW SEL1 ADV DDO SCK
V DD
V DD
NDI
DDI
WS
FID
39
28
27
6
31
33
DV
29
23
ER
35
34
15
16
14
SD
5
17
32
CK728 40
NICAM DECODER
V DD
I2 S
CK11648 42
DIGITAL FILTER
NOISE FILTER
3 DACDL 2 DACDR
RESET 24
SERIAL BUS
I 2 C INTERFACE
12 SCL 13 SDA
ABSOLUTE MAXIMUM RATINGS
Symbol VDD Ptot Toper Tstg Parameter Supply Voltage Total Power Dissipation Operating Temperature Range Storage Temperature Range Value 7 1.2 0, + 70 - 20, + 150 Unit V W o C o C
Symbol Rth (j-a) 2/12
Parameter Thermal Resistance Juntion-ambient
Max.
Value 67
o
Unit C/W
8204B-03.TBL
THERMAL DATA
8204B-02.TBL
8204B-02.EPS
41 36 37
TEST2 TEST1 TEST
25
MUTE
30
PDV
21
C1
20
C2
19
C3
18
C4
GND
GND
GND
TEST0
GND
US0
US1
US2
HA0
4 SERI
11
10
9
7
8
1 22
26 38
8204B-01.TBL
TDA8204B
ELECTRICAL CHARACTERISTICS (Tamb = 25oC, VDD = 5V, unless otherwise specified)
Symbol SUPPLY VDD IDD OUTPUTS DACDR, DACDL, SERI, US1, SCK, WS, C4, ER, DDO, FID, PDV, ADV, DV, CK728 VOL VOH Low Output Voltage (IOL = -4mA) High Output Voltage (IOH = 4mA) 0.4 0.7 VDD 0.4 2 - 10 V V V A mA Supply Voltage Range Supply Current 4.75 30 5 45 5.25 90 V mA Parameter Min. Typ. Max. Unit
US0 (open drain) VOL Low Output Voltage (IOL = -4mA) ILK High Output Current (leakage) CONSTANT CURRENT LED DRIVERS C1, C2, C3 Low Output Current (VOL = 0.4V) IOL INPUTS HA0, US2, RESET, DDI, SEL1, SEL0, TEST, NDI, CK11 VIL Low Input Voltage VIH ILK High Input Voltage Input Leakage Current RSW, MUTE Low Output Voltage (IOL = -4mA) High OUtput Voltage (IOH = 100A) Low Input Voltage SD Low Output Voltage (IOL = -4mA) High Output Voltage (IOH = 4mA) Low Input Voltage High Input Voltage Input Leakage Current 0.7 VDD 0.7 VDD 0.6 VDD
0.8 2
V V A
BI-DIRECTIONAL VOL VOH VIL VOL VOH VIL VIH ILK 0.4 0.8 0.4 0.8 0.6 VDD 2 V V V V V V V A
I2C INTERFACE VIL VIH fSCL tr, tf IIL CI VIL VIH tr, tf IIL CI VOL tf CI SCL Low Input Voltage High Input Voltage SCL Clock Frequency Input Rise and Fall Times Input Leakage Current (VI = 5.5V) Input Capacitance SDA Input Low Voltage Input High Voltage Input Rise / Fall Times Input Leakage Current (VI = 5.5V with output off) Input Capacitance Low Output Voltage (IOL = 3mA) Output Fall Time between 3.0V and 1.0V Load Capacitance 0 0 3 0 3 1.5 VDD 100 2 10 7 1.5 VDD 2 10 7 0.5 200 400 V V kHz s A pF V V s A pF V ns pF 3/12
8204B-04.TBL
TDA8204B
ELECTRICAL CHARACTERISTICS (continued)
Symbol I2C BUS TIMING tLOW tHIGH tSU, dAT tHD, dAT tSU, STO tBUF tHD, STA tSU, STA
2
Parameter SERIAL BUS (referred to VIH = 3V, VIL = 1.5V) Low Period Clock High Period Clock Data Set-up Time Data Hold Time Stop Set-up Time from Clock High Start Set-up Time following a Stop Start Hold Time Start Set-up Time following Clock Low to High Transition
Min.
Typ.
Max.
Unit
4 4 250 170 4 4 4 4
s s ns ns s s s
8204B-05.TBL 8204B-04.EPS 8204B-03.EPS
s
Figure 1 : I C Serial Bus Timing
SDA t BUF tF
t LOW
SCL t HD, STA tr t HD, DAT t HIGH t SU, DAT SDA t SU, STA t SU, STO
V IH = 3V, VIL = 1.5V
Figure 2 : I2S Bus Timing Diagram
I 2S CLOCK f = 896kHz
WS
f = 32 kHz
SD OUT
LSB
MSB
LSB
MSB
word n - 1 right channel
word n left channel 14 bits
word n + 1 right channel 14 bits
SD IN
MSB
LSB
MSB
4/12
TDA8204B
FUNCTION DESCRIPTION The TDA8204B is partitioned into 6 major parts shown in the block diagram. The NICAM Decoder performs data and sound re co ve ry f ro m t h e si g na l s sp e ci f ie d in EBU SPB 424. The expanded digital audio signals (14-bit) are made available at the digital audio interface (I2S) in a serial multiplex of left and right channels. They are also processed by a 4 times upsampling digital filter and noise shaper which results in a high speed digital data stream at the output pins DACDL/DACDR. This data stream can be applied to the 1-bit D-A convertors contained in the TDA8205. The TDA8204B is I2C bus controlled and provides control over the functions of the TDA8205 by means of a serial inter-chip bus. 1 - NICAM Decoder 1.1 - BLOCK DIAGRAM (see Figure 3) 1.2 - DESCRIPTION NICAM frame alignment requires searching out a frame alignment word (FAW) and a 16 frame sequence conveyed by C0 bit. Because of noise, interferences, errors in the incoming NICAM Data, aliases of the FAW, a robust scheme is implemented. It ensures the decoder will align, and stay aligned, to signals beyond the limit of maximum useable error rate. Thanks to a 511 bit PRBS synchronized by the recovered clock and a modulo 2 adder, original data are recovered. This data stream can be processed externaly for de-encryption in Pay TV applications using descrambled data Pins DDO, DDI. To allow simultaneous reading and writing of mono/stereo samples, de-interleaved data frames are stored in a 3 page RAM. Figure 3 : NICAM Decoder Block Diagram
DDO DDI RSW C1 C2 C3 C4 MUTE ER
The 10-bit input audio samples are expanded to 14-bit using scale factor bits according to NICAM decoding rules. Samples in error by the parity check are replaced by interpolated one or repeated. Mute is set according to an error counter when the error rate exceeds error rate limit (ERL) and reset when the error rate is below ERL/4. Application control information (bit C1, C2, C3, C4) is recovered by majority decision logic over 16 frames. the C1, C2, C3 , C4 bits can be read in SR0 register and are set on the C1, C2, C3, C4 pins according to the state of bit 0 (BEA) of the CR2 register. 2 - Digital Filter and Noise Shaper A digital filter performs 4X upsampling in two stages. The main FIR 2x upsampler is followed by a smaller 2x FIR upsampler. Digital upsampling means a much simpler post-DAC reconstruction filter can be used thus saving on external component count and cost. A noise shaper converts the samples from the digital filter into two high speed serial bitstreams which can be applied to the DACs in the TDA8205. 3 - I2S Bus A standard three-wire interface, conforming to the I2S bus protocol, is provided, allowing connection of an external DAC or DAT interface. Audio samples contain 14-bit, so 16-bit DACs will pad the two LSBs with 0. The word select clock operates at 32kHz and the serial clock at 896kHz. By setting SDI bit of CR2 to 1, the I2S interface can receive the digital I2S sound. This prevents duplicating the dual D/A converter.
28
27
21 20 19 18 6
23
25
MAJORITY LOGIC SCALE FACTOR RECOVERY 3 PAGE RAM EXPANDER ADDRESS
8204B-05.EPS
ERROR COUNTER
DESCRAMBLER
NDI 39 PDV 30 DV 33 FID 29 ADV 31
FRAME CONTROL
CONCEAL AND MUTE
GENERATOR
TO FILTER
5/12
TDA8204B
4 - Interchip Bus A one-line serial bus provides interchip communications allowing control of all functions through the single I2C bus interface. 5 - I2C Bus An I2C bus interface provides access to control and status registers within the two chips to allow control of their functions and monitoring of status. A digital filter is included to improve noise immunity. 5.1 - DATA FLAGS (see Figure 4) These indicate the status of the descrambled data on the DDO pin. They are inhibited if the decoder is out of alignement. - FID : Frame alignment word (scrambled) - PDV : Parity Data Valid. CIB0 and CIB1 overwrite the first 2 bits of FAW - ADV : 11 additional data bits - DV : Data valid (mode dependant) 5.2 - DECRYPTION (see Figure 5) The PRBS generator (used for descrambling) is normally preset to all ones at the start of each frame. However, it is possible to preset it to any value on each frame by means of a code word clock Figure 4 : Data Flags
1 FRAME
CK728 FA W DDO FID PDV ADV DV Stereo EVEN FRAME ODD FRAME
8204B-06.EPS 8204B-07.EPS
CB0 CB1
(CWC) and serial code word data (CWD) interface on pins SEL0 and SEL1. CWD, which is clocked in on the negative going edges of the CWC clock, can be sent anywhere during the frame except when FID = 1. The CWC is asynchronous with respect to the Nicam clock and the CWD will be used on the following frame. During the time FID = 1, the levels on the SEL0, SEL1 pins are read for language selection. Code words for descrambler presetting may be sent in either an 8-bit or 9-bit formats. There are four possibilities : - if 7 or less clock cycles are counted on CW-clock during a frame, the PRBS generator is preset to all ones ; - if 8 clock cycles are counted, 8 bits of CW-data are clocked into the shift register, the first bit of the previous transfer now moving to bit 9 position in the shift register. The resulting value is used to preset the PRBS generator on the next frame. - if 9 clock cycles are counted, the CW-data (which has been clocked into a 9-bit shift register) is used to preset the PRBS generator on the next frame. - if 10 or more clock cycles are counted, only the first 9 bits of the CW-data are used and loaded into the PRBS generator on the next frame.
NEXT FRAME
C0 C1 C2 C3 C4 AD0
AD10
NICAM DATA 704 BITS
24 CONTROL
704 DATA
DV Mono DV Data
Figure 5 : PRBS Presetter
FID
SEL0 (CWC) SEL1 (CWD)
6/12
TDA8204B
5.3 - SOFTWARE SPECIFICATION Software control of IC's is given by programming four registers, one read only status register (SR0) and three read and write control registers (CR1, CR2, CR3). Transmit format : S = Start, A = Acknowledge P = stop
S CHIP ADDRESS 0A REG SUB ADDRESS A DATA A P
Qn In G0 AUM
Output select (see tables) Input select (see tables) Auxiliary output gain, 0 = 0dB, 1 = 6dB Auxiliary output mute, 0 = no-mute, 1 = muted FRE : Free run clock VCXO for set up, 0 = normal, 1 = free run To set crystal series capacitor Switches and Matrix Description Figure 6
AMOR AMOL SAIR EAIR
: : : :
Receive format :
S CHIP ADDRESS 1A SR0 DATA A CR1 A DATA P
34
MAI
36 35
SAIL
32 31
38 37 27 AOL
Note : All registers are read sequentially; device status and the contents of all registers may be read. The sequence may be terminated by not acknowledging (NOACK) the slave.
EAIL
LFIL1
28 AOR
Chip address
8204B-08.EPS
1 MSB
0
1
1
0
1
HAO
R/W LSB
RFIL1
INTL
HAO : Hardware address selection pin Register addresses
Reg. Name SR0 CR1 CR2 CR3 Sub Adress 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 Function NICAM status Matrix and mutes NICAM control Switches Q1 0 0
Reserve sound switch
INTR Audio matrix
Output selection
Q0 0 1 Output AOL AOR
Mute and gain selection
Q0 0 0 1 1 I2 0 1 0 1 Mute OFF* ON* Gain 0dB** +6dB**
Register contents SR0 : NICAM status (read only)
US2 US2 MSB C1 0
*
C2 0
C3 0
C4 1
MUT 1
LA2 1
L/S 1 LSB
L/S :
LA2 : MUT : C4 : C3 : C2 : C1 : US2 :
If FN1 bit of CR2 is 0, LS bit is loss of frame alignment status LS =1, FAW is lost LS = 0 FAW is identified * If FN1 bit of CR2 is 1, LS bit is selected system status LS = 1, B/G standard LS = 0, I standard Loss of sub-frame alignment (1 = loss of alignment) NICAM mute (1 = DAC outputs muted) Reserve sound flag (1 = FM backup) Application control bit 3 Application control bit 2 Application control bit 1 User bit 2 (input) US2 bit indicates the state of US2 input Pin
Q0 0 I2 0 I1 0 I0 0 G0 0 AUM 0 FRE 0 LSB
* Mute is activated by left channel selection ** Gain is activated by right channel selection
Input selection
I1 0 0 1 1 I0 0 1 0 1 Input INTL INTR EAIL EAIR
CR1 : Matrix and mutes (read and write register)
Q1 0 MSB
Example of programming First : 00100X X X step INTL connected to AOL, mute ON on AOL/AOR Sec: 01011X X X ond EAIR connected to AOR, gain 0dB on step AOL/AOR Thrird : 0 0 0 0 0 X X X step INTL connected to AOL, mute OFF on AOL/AOR The power up default configuration is 0dB and unmute for both channels AOL/R, and INTL connected to AOL, and INTR connected to AOR.
7/12
TDA8204B
CR2 : NICAM control (read and write register)
SDI 0 MSB ECT 0 MAE 0 FN1 0 UMT 0 LA1 0 LA0 0 BEA 1 LSB
SDI ECT MAE FN1 UMT LA1 LA0 BEA
: I2S direction 0 = Output, 1 = Input : Bit error rate counting time 0 = 128ms, 1 = 64ms : Max allowed errors 0 = 511, 1 = 255 : Set function of bit 0 in SR0, 0 = loss of alignment (status), 1 = system status (I or B/G) : Un-mute NICAM, 1 = un-mute, 0 = mute : Language select 1 (LA1 SEL1) : Language select 0 (LA0 SEL0) : Set C1-C3 function
MAE 0 1 0 1 BER MUTE 8.9 x 10-3 (1 in 112) 4.4 x 10-3 (1 in 225) 1.8 x 10-2 (1 in 56) 8.9 x 10-3 (1 in 112)
applications. In order to know the status of the kit in stand-alone mode, consider the contents of the four I2C registers at power-ON (4 registers : SR0 - CR1 - CR2 CR3). Hardware configurable pins will be described later. 1 - Power-ON Configuration SR0 (status)
US2 US2 MSB C1 0 C2 0 C3 0 C4 1 MUT 1 LA2 1 L/S 1 LSB
ECT 0 0 1 1
US2 C1 C2 C3 C4 MUT LA2 L/S
Q1 0 MSB
Reserve Sound Flag DAC outputs muted (demuted as soon as NICAM appears) : the subframe alignment is been lost : FAW status (FN1 of CR2 = 0)
Q0 0 I2 0 I1 0 I0 0 G0 0 AUM 0 FRE 0 LSB
: : : : : :
Not used in stand-alone Application control bit status for NICAM signal
CR1 (R/W)
Un-mute at BER/4.
TDA8204B Output (Pin) C1 (21) C2 (20) C3 (19) BEA 0 C1* C2* C3* 1 Single mono mode Dual mono mode Stereo mode
* Application control bit of NICAM signal
Note : C4 pin remains unchanged. The function of C1-C4 in SR0 remains unchanged.
Q1 Q0 I2 I1 G0 AUM FRE
SDA 0 MSB
: : : : : : :
NICAM sound is sent on all matrix outputs and on AMOx pins Gain = 0dB on AMOx AMOx pins un-muted VCXO in normal mode
MAE 0 FN1 0 UMT 0 LA1 0 LA0 0 BEA 1 LSB
CR3 : Switches (read and write register)
US1 0 MSB US0 0 AUT 1 IBG 0 FS1 0 FS0 0 X 0 SYN 1 LSB
CR2 (R/W)
ECT 0
US1 US0 AUT IBG FSn SYN
: : : : : :
User bit 1 (output) User bit 0 (output) Automatic selection, 1 = enable Select system I or B/G, 1 = B/G Force switch (see table) 1 = synthesiser, 0 = dual VCXO (carrier loop)
FS0 0 1 0 1 Selection Auto NICAM FM-Mono FM-Stereo NICAM
SDA ECT & MAE FN1
: Normal mode : BER = 1/112
FS1 0 0 1 1
: Bit L/S of SR0 set to alignment loss status UMT : TDA8204B mute pin 25 to 0 LA1 : Result depending of SEL1 LA0 : Result depending of SEL0 BEA : Beacon decoding mode but all diodes are OFF until a NICAM signal has been found CR3 (R/W)
US1 0 MSB US0 0 AUT 1 IBG 0 FS1 0 FS0 0 X 0 SYN 1 LSB
NICAM STAND-ALONE APPLICATION The NICAM kit has been designed to be monitored by the I2C bus; nevertheless stand-alone working capability is offered to the designer for low cost
8/12
US1 US0 AUT
: Not used in stand-by mode : Not used in stand-by mode : Automatic standard
TDA8204B
IBG FSn FN2 SYN : Standard I (don't care) : Set to Auto NICAM (if NICAM fails, FM mono is selected) : Not used : Synthesizer selected As the I2C bus is not used LA0 and LA1 = 0 (power-ON condition) / SEL0 = Q0, SEL1 = Q1 The 4 choices are summarized in the table below.
SEL0 0 0 1 1 SEL1 0 1 0 1 DACDL M1 M1 M2 M2 DACDR M2 M1 M2 M1
2 - Hardware Configurable Pins 2.1 - TDA8204B - PIN 6 - (RSW) - as an output : status of the RSW switch - 0 = FM mono - 1 = NICAM - as an input : - 0 = FM mono (forced) 2.2 - TDA8204B - PINS 34/35 - (SEL0/SEL1) (see Figure 7) - to select the language in case of bilingual operation - selected value is related to LA0 and LA1 Figure 7
M1 = Mono 1 M2 = Mono 2 VII - 2.3. TDA8204B - PIN 25 - (MUTE) - as an output : status of the DAC - 0 = unmuted - 1 = muted - as an input : - 0 = unmute DAC (forced)
Q1 = SEL1 LA0 LA1 Q0 = SEL0
LA1 LA0
Q1 SEL1 34 Q0 SEL0 35
9/12
8204B-09.EPS
S W I T C H
C9 120pF
R8 150
C7 680pF
1 2 1
3
4
5
6
7
8
9
10 11 12 13 14 15
16 17 18 19 20
21
R19 270
R11 5.6k
R1 8.2k C17 100nF C4 1nF MON1 MON2 R12 5.6k L1 10H R20 22k L2 10H C23 10F
DD
R4 470 R16 1M C16 10F
F1 6.552MHz C13 100nF
C3 10nF
FM mono (forced)
single mono
Q1 C14 6.8nF C15 6.8nF
TRAP
R3 1.2k
R5 100
R6 33
C5 220pF C6 220pF
stereo
T1
6.0MHz C26 220F
C22 10F VCC
V
Q1, Q2 : BC109 or BC550C F1 : TOKO TH316BQM2110QDAF (5VFP) T1 : Matsushita EFCS6R0MWS X1 : 11.648MHz Crystal NDK
Unmute DAC (forced)
8204B-10.EPS
LED4
NICAM SYS. I IN R7 470 R13 43k R14 43k
10nF
C2 10nF
C18 100nF R15 5.6k
dual mono
LED3
C1
R2 470
BFP
LED2
10/12
FM MONO IN R L Language Selection C19 100nF C25 1F C24 1F LED1 mute C20 10F R17 330 C21 10F LK1 LK2 AUDIO OUTPUT ERROR MONITOR 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 42 41 40 39 38 22 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
TDA8204B
* C12 value depends on X1
C12 18pF*
X1
C11 150pF
11.648MHz
R10 39k
C10 6.8nF
42
APPLICATION DIAGRAMS Figure 8 : Stand Alone Application (I standard)
C7 100nF
R9 8.2M
C8 220nF
IC1
TDA8205
IC2
TDA8204B
2
3
4
5
6
7
8
9
10 11 12 13 14
15 16 17 18 19
20 21
R18 10kW Q2
C28 100nF
* C23 value depends on X1
EXTERNAL AUDIO IN Left Right FM MONO IN C13 100nF C14 10F C15 10F C16 1F C17 1F C18 10F C19 10F C11 100nF C12 100nF
STEREO AUDIO IN Right Left
AUDIO MUTABLE OUT Left Right
AUDIO OUTPUT Right Left
CK728
TEST
SEL0
SEL1
DV
ADV
PDV FID
LED1 mute R25 330 ERROR MONITOR
VDD
C23 18pF *
X1
C22 150pF
11.648MHz
R1 39k
C21 6.8nF
VCC 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
R27 8.2M
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
C25 220nF
C26 120pF
R2 150
R32 270
IC1
TDA8205
IC2
TDA8204B
MUTE
C9 100nF VDD
C10 100nF
V DD 1 2 3 4
C45 680pF
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 1 2 3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
R31 10k Q3
R23 5.6k
LED2 single mono C42 100nF C43 100nF
Figure 9 : I2C Bus Controlled Application (I and B/G standard)
R6 8.2k C37 1nF
VDD
R5 470 R24 1M C20 10F
C32 10nF
F1 5.85MHz C39 100nF
LED3 dual mono LED4 stereo SDA SCL
C31
R17 470 C40 6.8nF C44 220F +12V C38 1nF C1 10F C2 100nF C3 100nF C4 100nF VDD MON1 MON2 +5V C5 10F C6 100nF C7 100nF C8 100nF R33 22k C41 6.8nF R19 5.6k R21 43k R22 5.6k
R7 470
BFP
Q1
NICAM SYS. BG IN
10nF
C33 10nF
R20 43k
TRAP
R8 1.2k
R9 100
R10 33
I 2 C BUS
T1
C4
C3
C2 GND
VCC USER BITS
I 2 S BUS
SD
US1
US0
R12 8.2k
R11 470
F2 6.552MHz
RSW
SCK
WS
CONTROL BITS
C35 10nF
C34
R18 470
R13 470
BFP
NICAM SYS. I IN
Q2
10nF
C36 10nF
R14 1.2k C30 220pF C29 220pF
R15 100
R16 33
T2
Q1, Q2, Q3 : BC109 or BC550C F1 : TOKO TH316 BQM 2080 QDAF (5VFP) F2 : TOKO TH316 BQM 2110 QDAF (5VFP) T1 : Matsushita EFCS5R5MWS T2 : Matsushita EFCS6R0MWS X1 / 11.648MHz Crys tal NDK
6.0MHz
C1
5.5MHz
TRAP
TDA8204B
11/12
8204B-11.EPS
TDA8204B
PACKAGE MECHANICAL DATA 42 PINS - PLASTIC SHRINK
e4 F
a1 A I
b2
b e
e
Stand-off
L
b1
E
D
42
22
1
21
Dimensions A a1 b b1 b2 b3 D E e e3 e4 F i L
Min. 3.30
Millimeters Typ. 0.51 0.35 0.20 0.75 0.75 15.57
Max.
Min. 0.130
Inches Typ. 0.020 0.014 0.008 0.030 0.030 0.613
Max.
0.59 0.36 1.42 39.12 17.35 0.070 1.400 0.600
0.023 0.014 0.056 1.540 0.683
1.778 35.56 15.24 14.48 5.08 2.54
0.100
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1994 SGS-THOMSON Microelectronics - All Rights Reserved Purchase of I2C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips. SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
12/12
SDIP42.TBL
0.570 0.200
PMSDIP42.EPS

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